This invention relates to an addressable matrix device comprising a panel having a row and column matrix array oi addressable elements and driving means for addressing the elements via sets of row and column address conductors of the panel, the driving means comprising a row address conductor drive circuit and a column address conductor drive circuit at least one of which comprises sequence generating means having a plurality of output stages associated with respective address conductors in a group of successive address conductors.
The invention is concerned especially, but not exclusively, with matrix display devices for example comprising liquid crystal picture elements.
The invention is concerned also with addressable matrix devices generally, for example sensing devices comprising an array of addressable touch sensing or light sensing elements, or memory devices comprising a matrix array of addressable memory locations and having a memory element at each, or selected, locations.
Conventionally, matrix liquid crystal display devices comprise a row and column array of picture elements which are addressed via sets of row and column address conductors connected respectively to row and column driver circuits supplying scanning and data signals. In a typical active matrix addressed display device the row driver circuit comprises a sequence generating means in the form of a shift register circuit operable to apply a selection signal to each conductor in sequence. The column driver circuit sequentially samples a video line to store data in storage elements, e.g. capacitors, associated with the column address conductors, and includes sequence generating means comprising a shift register circuit which operates respective column switches sequentially to transfer the video data to the storage elements connected to the column conductors.
It will be appreciated that for TV displays and the like large numbers of row and column address conductors are needed to address the required number of picture elements, typically several hundreds of thousands for a medium resolution TV display. This in turn necessitates large numbers of connections between the address conductors and driver circuits if external driver circuits, for example in the form of separate chip packages, are used. This large number of connections causes to problems, not only in construction but in reliability as well.
Similar problems are experienced with other types of addressable matrix devices, for example sensing devices comprising a row and column array of sensing elements, such as touch sensitive or light sensitive elements, addressable via row and column address conductors, for example as described in GB-A-2232251 and U.S. Pat. No. 4345248, or memory devices comprising a row and column array of memory locations addressable via column and row address conductors, for example as described in EP-A-117045 or EP-A-367152. Such devices can be driven in a similar manner with the elements being addressed by a row driver circuit which selects each row of elements in turn and a column driver circuit which is operable to drive and/or sense the condition of each element in the row.
In U.S. Pat. No. 4952031 there is described a matrix liquid crystal display device which is intended to be connected with other similar display devices to form a large area display and in order to simplify interconnections between adjacent display devices an electro-optic switching arrangement is used to drive the sets of row and column address conductors. Each address conductor of one set provided on a substrate is connected to a signal bus carried on the same substrate via a respective optically-activated switch. An array of light emitting devices, one for each optically-activated switch, is provided on a separate substrate disposed adjacent the substrate carrying the set of conductors and by operating each light emitting device in turn, each of the address conductors can be connected in sequence with the signal bus by activation of its associated switch. As a separate light emitting device is required for each optically-activated switch, the number of light emitting devices required is considerable, corresponding to the number of address conductors in the set. The number of light emitting devices entailed imposes limitations on the physical lay-out of the address conductors and optically-activated switches. Furthermore, in order to energise the light emitting devices individually an equivalent number of external connections to a drive circuit, for example, a shift register circuit, are required so that similar problems to those described above result, as well as problems with ensuring that the light emitting devices are optically well coupled with the light activated switches on an individual basis without cross-talk.